In apparatus for receiving incoming synchronous data signals, it is advantageous to generate periodic clock pulses having a fixed relationship to the pulses of the incoming data. To achieve a desired relationship, the clock pulses may be derived from the data by utilization of a phase-locked loop circuit. Traditionally, a phase-locked loop circuit comprises a phase detector for comparing the phase of an input signal and a clock signal to generate an error signal representative of the magnitude of the phase difference. This error signal, after being filtered in a low pass filter, is applied to a controllable clock oscillator, thereby modifying the frequency of the clock signal to minimize the phase difference. In one typical prior art system, a data signal is applied to a differentiating circuit followed by a rectifier and a monostable multivibrator, to produce a pulse for each transition of the data signal. The pulse signal is used to increment or decrement a counter which, in turn, is used to control a divider circuit connected to a pulse generator for modifying the output signal of the pulse generator. However, when several circuits are connected essentially in a serial string, as in the prior art, a significant delay may be introduced in the chain. At high data frequencies, a significant phase difference between clock and data signals may occur before the clock signal can be modified.